Welcome to the
The world is changing. The advances in microelectronics are
changing the technology. One die can contain several billion transistors. This
makes it possible, if not inevitable, to map into one die several processor
cores. Also, the microelectronics market is changing. There is estimation that
in the near future, in 2010, about 90% of applications are embedded systems,
most of these are mobile, wireless consumer appliances that must be small in
size, with very low power consumption and with high performance.
This will emerge changes in the
design concepts of microelectronic devices, the design concepts of
application-specific processors, as well as general-purpose processors. Many
companies and researchers believe that the challenge for future is to use reconfigurablilty and parallelism, introducing configurable
multiprocessing on a single die. The reconfiguring is migrating from the
circuit level to the level of algorithms, while hundreds, if not thousands,
simple processor-cores are replacing complex processors on a single die.
Configurable parallel processing has
many advantages. First, it replaces time-consuming digital design by
programming of multiprocessors reducing, thus, the design cost and time, and, makes
the design reprogrammable. Second, algorithms are mapped directly onto
configurable space of simple processors achieving the efficiency of
Application-Specific Integrated Circuits (ASICs).
Third, the multiprocessor concept facilitates the building of energy efficient
systems using dynamic shutdown of unused processors. And last, the performance
is scalable and depends on the algorithmic design, on the number of processors
involved and not on the clock frequency of electrical circuits.
The international conference on
Engineering of Reconfigurable Systems and Algorithms (
Conference Chair
Dr Toomas P Plaks
LSBU,
