Neuchatel, Switzerland
   12-13 February, 2001
 

   Workshop Programme

18:00 Reception and Registration

08:30 Registration
09:00 Welcome by Christian Piguet

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09:15-10:15    Session 1: Asynchronous Interconnect I

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09:15 Ad Peeters
"Tangram Handshake Channels" (abstract)(slides)

09:45 Joep Kessels
"Designing an asynchronous Bus Interface" (abstract)(slides)
 

10:15-10:35 Coffee Break

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10:35-12:20    Session 2: Asynchronous Decoupling

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10:35 Simon Moore
"Channel Communication Between Independent Clock Domains" (abstract)(no slides)(paper)

11:05 David Kinniment
"Synchronizer circuit performance" (abstract)(slides)

11:30 Alex Yakovlev
"Hets: towards harmony of time and power in systems on chip" (abstract)(slides)

11:55 Ian G. Clark
"Modelling and analysis of asynchronous communication mechanisms" (abstract)(slides)

12:20-14:00 Lunch Break + Closed Session: ACiD-WG Technical Management Committee Meeting

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14:00-15:00    Session 3: Asynchronous Interconnect II

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14:00 John Bainbridge
"1-of-4 Encoded Global Asynchonous Interconnect" (abstract)(slides)

14:30 Mark Josephs
"Self-Timed On-Chip Packet-Routing" (abstract)(slides)
 

15:00-15:30 Coffee Break

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15:30-17:00    Session 4: Asynchronous Design Projects

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15:30 Thomas Villiger
"A Globally-Asynchronous Locally-Synchronous VLSI Circuit for the SAFER Cryptoalgorithm" (abstract)(slides)

16:00 Frederic Robin
"An Asynchronous IDCT block using Quasi Delay Insensitive Logic and its comparison to a synchronous equivalent" (abstract)(slides)

16:30 Gottfried Zojer
"Asynchronsparc" (abstract)(no slides)

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17:00-17:45    Session 5: Discussion

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17:00 Christoph Heer (Chair)
"Is asynchronous circuit design ready for widespread industrial use ?" (opening slide)(subsequent discussion)

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18:00 Visit to the Cathedral and Castle
19:00 Welcome by the Government of Canton of Neuchâtel
20:00 Dinner

08:00 Closed Session: ACiD-WG Technical Management Committee Meeting

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09:00-11:00    Session 6: Asynchronous Implementation of Petri Nets

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09:00 Helmut Baur
"A Fast Petri Net Based Programmable Controller: From the Specification to a Self-Timed Implementation" (abstract)(slides)

09:30 Josep Carmona
"A structural encoding technique for the synthesis of asynchronous circuits" (abstract)(slides)

10:00 Christian Piguet
"Design of Dynamic Asynchronous Flip-Flops and Counters based on Dynamic STG" (abstract)(slides)(paper)

10:30 Alexander Smirnov
"A Technique to Automate STG Analysis and Refinement for CSC and Normalcy" (abstract)(slides)
 

11:00-11:30 Coffee Break

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11:30-12:30    Session 7: Verification and Test of Asynchronous Circuits

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11:30 Michael Yoeli
"LOTOS-based Verification of Modular Asynchronous Circuits" (abstract)(slides)( Technical Reports CS-2001-08 and CS-2001-09)

12:00 Frank te Beest
"Testing Asynchronous Circuits in a Synchronous Environment" (abstract)(slides)

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12:30 Closing Remarks by Mark Josephs
12:45 Lunch