OF THE EUROPEAN COMMISSION'S FIFTH FRAMEWORK PROGRAMME

Munich, Germany

28-29 January, 2002

Monday 28^th of January 2002:

08:30 Registration

09:00 Welcome by Christoph Heer
(slides)

9:15 - 10:45 Session 1: Design Methods/Tools I (Chair: S. Moore)

• S.F. Nielsen, J. Sparsų, J. Madsen, J.P. Hammerstoft, J.S. Jensen
  "High-level synthesis of asynchronous circuits from control data flow graph representations"
  (abstract) (photo 2) (photo 3) (slides)
• I. Blunno, L. Lavagno
  "Designing an asynchronous microcontroller using Pipefitter"
  (abstract) (slides)
• A.V. Dinh Duc, J.B. Rigaud, A. Rezzag, A. Sirianni, J. Fragoso, L. Fesquet, M. Renaudin
  "TAST CAD Tools"
  (abstract) (slides)

10:45 - 11:15 Coffee Break

11:15 - 12:45 Session 2: Design Methods/Tools II (Chair: L. Lavagno)

• S. M. Nowick, T. Chelcea, A. Bardsley, D. Edwards
  "A Burst-Mode Oriented Back-End for the Balsa Synthesis System"
  (abstract) (slides)
• M.B. Josephs, D.P. Furey
  "Asynchronous design using the DISP programming language and the tools di2pn and petrify"
  (abstract) (slides)
• A.Yakovlev, F. Burns, A. Bystrov, A. Koelmans, R. Krenz, D. Shang
  "Behavioural synthesis of asynchronous controllers: a case study with a self-timed communication channel"
  (abstract) (slides)

12:45 - 14:00 Lunch Break

14:00 - 15:00 Session 3: Novel Implementation Techniques (Chair: J. Sparsų)

• J. Kessels, A. Peeters, P. Wielage, S.J. Kim
  "Clock Synchronization through Handshaking"
  (abstract) (slides)
• R. Ginosar, Y. Elboim, A. Kolodny
  "A Clock Tuning Circuit for System-on-Chip"
  (abstract) (slides)

15:00 - 15:45 Session 4: Poster Introduction (9 x 5 min, Chair: E. Grass)

• G. Taylor, R. Mullins, S. Moore
  "Exploiting both periodicity and asynchrony"
  (abstract) (slides)
• T. Villiger, F. Gurkaynak, S. Oetiker, H. Kaeslin, N. Felber, W. Fichtner
  "Multi-point Interconnect for Globally-Asynchronous Locally-Synchronous Systems"
  (abstract) (slides)
• S. Fairbanks, S. Moore
  "The Distributed Clock Generator"
  (abstract) (slides)
• S. Oetiker, T. Villiger, F. Gurkaynak, H. Kaeslin, N. Felber, W. Fichtner
  "High Resolution Clock Generators for Globally-Asynchronous Locally-Synchronous Designs"
  (abstract) (slides)
• J. Carmona, J. Cortadella
  "I/O Compatibility of Reactive Systems"
  (abstract) (slides)
• A. Romero
  "NCL-DES: An asynchronous DES encryption chip on NCL logic"
  (abstract) (slides)
• D. Panyasak, M. Renaudin, G. Sicard
  "Shaping Current Profile of Asynchronous Circuits"
  (abstract) (slides)
• F. Bouesse, L. Fesquet, M. Renaudin
  "QDI Circuits to Improve Smartcard Security"
  (abstract) (slides)
• B. Sarker, E.Grass, K. Maharatna
  "Asynchronous CORDIC Processor Implementation"
  (abstract) (slides)

15:45 - 16:30 Poster Viewing and Coffee Break

16:30 - 18:00 Session 5: Design Flows (Chair: A. Peeters)

• C. Cuche, C. Piguet, V.G. Oklobdzija
  "Design Flow and CAD tools for asynchronous design of sequential library cells
  (abstract) (slides)
• C. Sotiriou
  "Implementing Asynchronous Circuits using a Conventional EDA Tool Flow"
  (abstract) (slides)
• E. Campbell
  "Embed with clocked logic - An industry example of integrating clock-free circuitry within an ASIC designed using a standard synchronous design flow "
  (abstract) (slides)

19:30 Dinner at a small brewery located in a former Bavarian railway station
(photo 4) (photo 5) (photo 6) (photo 7) (photo 8)

Tuesday 29^th of January 2002:

08:30 - 10:00 Session 6: Verification and Test (Chair: C. Piguet)

• D.J. Kinniment, O.V. Maevsky, A. Bystrov, G. Russell, A.V. Yakovlev
  "On-chip test for timing conditions"
  (abstract) (slides)
• M.A. Pena, J. Cortadella, E. Pastor, A. Smirnov
  "Formal verification of a complex timed circuit: IPCMOS"
  (abstract) (slides)
• F. te Beest, A. Peeters, K. van Berkel, H. Kerkhoff
  "Optimizing Scan Test for Asynchronous Circuits"
  (abstract) (slides)

10:00 - 11:00 Session 7: Keynote Speaker (Introduction: C. Heer)

• S. Furber
  "Industrial take-up of asynchronous design"
  (slides 1) (slides 2)

11:00 - 11:30 Coffee Break

11:30 - 12:30 Session 8: Invited Speakers (Introduction: C. Heer)

• D. Ferguson, M. Hagedorn
  "The Application of NULL Convention Logic to Microcontroller/Microconverter Products"
  (abstract) (slides)
• S. M. Nowick
  "MINIMALIST: A CAD Environment for the Synthesis and Optimization of Burst-Mode Asynchronous Controllers"
  (abstract) (slides)

12:30 - 13:00 Presentation of Methods/Tools Report and Closing Remarks by Mark Josephs

13:00 - 14:00 Lunch Break

14:00 - 16:00 Closed Session: ACiD-WG Technical Management Committee Meeting