Periodic Progress Report
(May 1997 - April 1998)
Working Group 21949 (ACiD-WG)
Asynchronous Circuit Design
MB Josephs (Project Manager)
Centre for Concurrent Systems and VLSI, School of CISM, South Bank University (SBU), London, UK
J Cortadella
Department of Software, University Polytechnic of Catalonia (UPC), E
SB Furber
Department of Computer Science, University of Manchester (MU), UK
L Lavagno
Department of Electrical Engineering, Polytechnic of Turin (PT), I
M Renaudin
Department of Electronics, National Higher School of Telecommunications (TB),
Brittany, F
J Sparsoe
Department of Information Technology, Technical University of Denmark (DTU), Lyngby, DK
JT Udding
Department of Computing Science, University of Groningen (RuG), NL
K van Berkel
IC Design Centre, Philips Research Laboratories (PRL), Eindhoven, NL
T Verhoeff
Department of Mathematics and Computing Science, Eindhoven University of Technology (TUE), NL
AV Yakovlev
Department of Computing Science, University of Newcastle (NU), UK
Contents
The specific objectives of the Working Group in the Fourth Framework, as stated in
Annex 1 of Contract No. 21949, were to
- facilitate the work of the ten European scientists who form its Technical
Management Committee (TMC) and their research teams by providing financial
support for European and international travel;
- organize European workshops for regular exchange of information and discussion
between teams, covering the costs of invited speakers where appropriate;
- organize European teaching and training activities aimed at university students,
young researchers and practising engineers;
- support the research work or training of European scientists and engineers from
other teams by inviting them to our events, covering their costs where appropriate;
- support a European bid to host Async'97, the Third International Symposium on
Advanced Research in Asynchronous Circuits and Systems, with an offer of 10K
ECU of financial sponsorship (Async'94 and Async'96 were held in Utah, USA,
and in Aizu, Japan, respectively).
We also committed ourselves to make every effort to establish and build upon
contacts within the European semiconductor industry and other related industries with
a view to better understanding their needs and to facilitating technology transfer.
In this report we describe the activities of the Working Group during its second year
of operation under this contract. Travel and subsistence costs were claimed
(objective 1) for European travel to
- our summer school and workshop
- CHDL'97
- two UK Asynchronous Forums organized in cooperation with ACiD-WG
- miscellaneous meetings
and for international travel to the conferences
- Async'98
- 34th DAC
- CSD'98.
In the first year a workshop was hosted by RuG; this year a workshop was hosted by
PT (objective 2). A summer school was also hosted by DTU (objective 3). In each
case, financial support was given to European participants who were not members of
the Working Group (objective 4). Objective 5 was met last year when TUE hosted
Async'97; also, as indicated in last year's report, the Working Group offered to
sponsor Async'99 if UPC were to host it, and we can now confirm that this bid has
been accepted by the Async steering committee.
TMC members would be interested in extending the current three year contract into a fourth
year.
Members of the TMC have continued to solicit "letters of interest" in the Working
Group from new contacts in industry as they have become established. Last year we
reported that we had 10 such industrial affiliates; this year we were able to add three
more, namely,
- Alcatel Telecom, B
- Hellenic Aerospace Industry, G
- MITEL Semiconductor, UK
The Project Manager ensures that industrial affiliates are kept informed of and invited
to forthcoming ACiD-WG events. Proceedings were also sent to those affiliates who
were unable to send representatives to the ACiD-WG Workshop in January 1998.
The first group of 17 design experiments launched under the Esprit Electronic System
Design - Low Power Design initiative included three that are related to the theme of
the Working Group:
- 25519 DESCALE, involving PRL
- 25242 PREST, involving MU and MITEL Semiconductor
- 25249 AMIED, involving Hellenic Aerospace.
PRL disclosed at Async'98 that a project in collaboration with TUE and Philips
Semiconductors, Zurich, had used Tangram to implement the 80C51 microcontroller
and demonstrated a factor of 4 power advantage compared to a recent synchronous
implementation in the same 0.5 micron CMOS process.
Industrial affiliate, Cogency Technology, disclosed at Async'98 that they had
developed a self-timed DSP core, part of a fax/modem chip, for LG Semicon, Korea.
A 47% power reduction had been measured compared to the synchronous part
fabricated in the same 0.6 micron, 5V CMOS process.
There was a successful outcome to the joint project between DTU and industrial
affiliate, LSI Logic, Denmark, mentioned in last year's report, in which the TR4101
embedded microprocessor core was to be re-implemented. At the first attempt and
with only 1 man-year of effort, they were able to achieve a somewhat better power-
efficiency (635 MIPS/Watt) than the commercial design, again demonstrating the
viability of asynchronous design as a route to low power consumption.
The Petrify logic synthesis tool, developed by UPC, PT, NU and the University of
Aizu, is being used by MU, DTU and Cogency in their design work. PT have also
released an experimental version of a tool that translates from Verilog HDL into
STGs.
Collaboration between RuG and industrial affiliate, Hollandse Signaalapparaten,
continues, as does collaboration between RuG, TUE and Sun Microsystems
Laboratories, USA. Progress is being made in providing tool support for the formal
methods of SBU, RuG and TUE so that they may be applied to the specification and
decomposition of components and subsystems.
Discussions were held between industrial affiliate, MATRA British Aerospace, SBU
and NU concerning possible future collaboration.
The Project Manager continues to keep up to date the home page of ACiD-WG on the
World Wide Web at URL
"http://www.scism.sbu.ac.uk/ccsv/ACiD-WG/".
The aim of the summer school was to stimulate experimentation with and application
of methods and tools for the design of asynchronous circuits. The target audience
comprised (1) Ph.D. students from Computer Science and Electrical Engineering
departments, and (2) researchers, architects and designers in the electronics industry.
The summer school provided insight into and hands on experience with state-of-the-
art design methods and CAD-tools for asynchronous design.
Rather than attempting a comprehensive coverage of the field, the summer school
lectures provided in depth coverage of a few of the more significant approaches to
asynchronous design. There was plenty of opportunity for hands-on experience with
the associated CAD tools. Furthermore, the summer school was planned as one
coordinated event where the different parts complemented each other. The program
reflected a bottom up approach to asynchronous design with a significant element of
practical CAD-tool laboratories. (Note also that information about the Esprit Design
Clusters action was distributed to attendees.)
TMC members Cortadella, Furber, Van Berkel and Sparsų lectured, together with
Kishinevsky (Aizu), Kessels (PRL) and Van Gageldonk (TUE). The number of
"students" exceeded our target of 50, with nearly a quarter coming from industry.
Most European countries were represented, with a minority of attendees coming from
other continents.
The success of the summer school is also evident from the results of a questionnaire
that was distributed to attendees: it appears that all attendees had a good overall
impression of the event and the majority had their needs well satisfied. In retrospect, a
little less time might have been spent on practical sessions using TANGRAM
(because it was not available for use outside the school), and a little more time could
have been spent addressing circuit design issues, including testing.
29 participants from 16 institutions attended the Turin workshop. 8 out of the 10
member organizations of ACiD-WG were represented, together with two industrial
affiliates, MATRA BAe Dynamics and CSEM. Three European universities that are
not members of ACiD-WG, a Canadian university and a Japanese university were also
represented. Finally, Intel, USA, sent a delegate from their Strategic CAD Labs.
The first day concentrated on specification models and languages. It began with a
tutorial on VHDL by Protheroe (SBU). He indicated how asynchronous designs (e.g.
Petri net descriptions) might be expressed in VHDL and simulated. Indeed a
subsequent presentation by a member of Renaudin's team at TB explained how they
had gone about translating Prof. Martin's CHP notation into VHDL for the purpose of
asynchronous-design simulation. Endecott (MU) pointed out the deficiencies of
VHDL and other modelling languages, and presented the LARD language as an
alternative. These different views were discussed further at the end of the day, as was
the possibility of translating between AND/IF (as used in tools development at TUE
and RuG) and the format accepted by UPC's Petrify tool.
The challenge of modelling an asynchronous version of Hennessy & Patterson's DLX
microprocessor was taken up in three presentations, and these served to illustrate the
use of Handshake Algebra, Petri nets and Tangram. Other presentations addressed
timing constraints, formal analysis of specifications, handshake expansion, and
mixed-mode pipelines. Finally, Josephs talked about some asynchronous design
experiments recently funded under the Esprit Low Power Design Cluster initiative and
encouraged attendees to submit further proposals.
The theme of the second day was technology effects on asynchronous design. It
opened with a presentation on the 1997 SIA Technology Roadmap, which mentions
"asynchronous" explicitly as as a means of attaining the predicted performance targets
for the year 2005. Other presentations were concerned with logic synthesis techniques
and layout. These included the approach followed by Piguet (CSEM) in the design of
a low-power cell library that has been used in commercial products. Again, the
presentations were followed by a lively discussion.
The proceedings of this workshop are available both as a PT Technical Report and on
the World Wide Web at URL
"http://polimage.polito.it/acid/".
MU presented a paper (which appears in the list of publications in last year's Periodic
Progress Report) at the Thirteenth International Conference on "Computer Hardware
Description Languages and Their Applications". A trip report
is linked to the ACiD-WG home page on the World Wide Web. The MU paper describes the BALSA
language, which is similar to TANGRAM, and the development of the front-end of a
compiler for that language. An up to date description of Balsa can be found in
Bardsley's M.Sc. thesis, April 1998.
UPC presented two papers at the 34th Design Automation Conference. A
trip report is
linked to the ACiD-WG home page on the World Wide Web
Meetings between RuG (Greenboom and Udding) and Hollandse Signaalapparaten, as
mentioned in last year's Periodic Progress Report, have continued this year.
This series of meetings has continued, with MU, NU and SBU among the UK
universities taking part. Cogency and MATRA British Aerospace were represented at
the Second Forum.
A third special interest group meeting was held, this time on the themes of "Efficient
Analysis of Petri Nets" and "Reactive Transition Systems", involving Lavagno and
Cortadella. Again, a report of the research work
undertaken at this meeting is linked to the ACiD-WG home page on the World Wide Web.
Josephs visited MATRA British Aerospace.
MU, NU and SBU participated in a meeting organized by the UK EPSRC in which the
portfolio of projects in Electronics funded by the research council was reviewed.
Verhoeff visited RuG.
Lavagno and Cortadella attended this International Conference on "Applications of
Concurrency to System Design" to present a paper and give a tutorial. A
report was
prepared by Lavagno and is linked to the ACiD-WG home page on the World Wide
Web. Lavagno extended his stay for two weeks in order to undertake collaborative
research on the optimization under timing assumptions of speed-independent circuits.
The Fourth International Symposium on Advanced Research in Asynchronous
Circuits and Systems took place in California. Attendance was at a similar level to
1996, but this time 70% of participants were from North America rather than from
Europe. Seven members of the TMC (co-)authored papers and three chaired sessions.
A trip report
is linked to the ACiD-WG home page on the World Wide Web.
Pessolano (SBU) visited TB. A report of the discussions that took place at this
meeting is linked to the ACiD-WG home page on the World Wide Web. SBU have
installed TB's CHP2VHDL tool for evaluation.
The following articles by members of ACiD-WG were published during the second
year of the contract. They are grouped according to the affiliation of their
co-authors:
NU:
- D.J. Kinniment, B. Gao, A. Yakovlev, F. Xia,
Towards asynchronous A-D conversion,
Proc. Async'98, March-April 1998, San Diego, CA, IEEE CS Press, pp. 206-215.
- A. Yakovlev,
Designing Control Logic for Counterflow Pipeline Processor Using Petri nets,
Formal Methods in Systems Design 12(1):39-71, Kluwer, 1998.
- A. Semenov,
Verification and Synthesis of Asynchronous Control Circuits using Petri Net Unfoldings,
PhD Thesis, University of Newcastle upon Tyne, July 1997.
- M. Pietkiewicz-Koutny,
Transition systems of elementary net systems with inhibitor arcs,
Proc. Int. Conf. on Applications and Theory of Petri Nets (ATPN'97),
Toulouse, June 1997, LNCS 1248, Springer-Verlag, pp. 310-327.
NU and Kings College, London:
- I.G. Clark, F. Xia, A.V. Yakovlev, A.C. Davies,
Petri net models of latch metastability,
Electronics Letters 34(7):635-636, 1998.
NU and UPC:
- A. Semenov, A. Yakovlev, E. Pastor, M.A. Pena, J. Cortadella,
Synthesis of Speed-Independent Circuits from STG-Unfolding Segment,
Proc. 34th Design Automation Conference (DAC'97), Anaheim, USA, June 1997, pp. 16-21.
NU, PT, UPC and University of Aizu:
- A.Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, A.Taubin, A. Yakovlev,
Identifying state coding conflicts in asynchronous system specifications using Petri net unfoldings,
Proc. Int. Conf. on Appl. of Concurrency to System Design (CSD'98), March 1998, Aizu-Wakamatsu,
Japan, IEEE CS Press, pp. 152-163.
- J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, E. Pastor, A. Yakovlev,
Decomposition and technology mapping of speed-independent circuits using boolean relations,
Proc. IEEE/ACM Int. Conf. on CAD (ICCAD'97), November 1997, IEEE CS Press.
- J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Yakovlev,
A region-based theory for state assignment in speed-independent circuits,
IEEE Trans. on CAD 16(8):793-812, 1997.
- M. Kishinevsky, J. Cortadella, A.Kondratyev, L. Lavagno, A.Taubin, A. Yakovlev,
Coupling asynchrony and interrupts: place chart nets and their synthesis,
Proc. Int. Conf. on Applications and Theory of Petri Nets (ATPN'97),
Toulouse, June 1997, LNCS 1248, Springer-Verlag, pp. 328-347
UPC:
- O. Roig, J. Cortadella, M.A. Pena, E. Pastor,
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits,
Proc. 34th Design Automation Conference (DAC'97), Anaheim, USA, June 1997, pp. 620-625.
SBU and University of Pisa:
- F. Pessolano, R. Mariani, R. Saletti,
An innovative multi-valued asynchronous approach to system design,
Proc. 7th Int. Workshop on Power, Timing, Modelling, Optimisation and Simulation (PATMOS'97),
Louvain, September 1997.
SBU and TUE/University of Oxford:
- M.B. Josephs, A.M. Bailey,
The Use of SI-Algebra in the Design of Sequencer Circuits,
Formal Aspects of Computing 9:395-408, Springer-Verlag, 1997.
TUE:
- T. Verhoeff,
Analyzing Specifications for Delay-Insensitive Circuits,
Proc. Async'98, March-April 1998, San Diego, CA, IEEE CS Press, pp. 172--183.
PRL and TUE:
- K. van Berkel, H. van Gageldonk, J. Kessels, C. Niessen, A. Peeters, M. Roncken, R. van de Wiel,
Asynchronous Does Not Imply Low Power, But ...,
A. Chandrakasan, R. Brodersen (eds) Low Power CMOS Design, IEEE Press, 1998.
PRL, TUE and Philips Semiconductors:
- H. van Gageldonk, D. Baumann, C.H. van Berkel,
D. Gloor, A. Peeters, G. Stegmann,
An Asynchronous Low-Power 80C51 Microcontroller,
Proc. Async'98, March-April 1998, San Diego, CA, IEEE CS Press, pp. 96-107.
PRL and University of Waterloo:
- R. Negulescu, A. Peeters,
Verification of Speed-Dependences in Single-Rail Handshake Circuits,
Proc. Async'98, March-April 1998, San Diego, CA, IEEE CS Press, pp. 159-170.
RuG:
- W.C. Mallon, J.T. Udding,
Building Finite Automata from DI Specifications,
Proc. Async'98, March-April 1998, San Diego, CA, IEEE CS Press, pp. 184-193.
DTU:
- L.S. Nielsen, J. Sparsoe,
An 85 microwatt Asynchronous Filter-Bank for a Digital Hearing Aid,
Proc. IEEE Int. Solid State Circuits Conf., 1998, pp. 108-109.
- L.S. Nielsen,
Low-power Asynchronous VLSI Design,
PhD Thesis, IT-TR:1997-12, 1997.
DTU and LSI Logic Denmark:
- K.T. Christensen, P. Jensen, P. Korger, J. Sparsoe,
The Design of an Asynchronous TinyRISC TR4101 Microprocessor Core,
Proc. Async'98, March-April 1998, San Diego, CA, IEEE CS Press, pp. 108-119.
TB and France Telecom:
- F. Robin, G. Privat, M. Renaudin,
Asynchronous Relaxation of Morphological Operators : a Join Algorithm-Architecture Perspective,
Int. Journal of Pattern Recognition and Artificial Intelligence (IJPRAI) 11(7):1085-1094, 1997.
- M. Renaudin, P. Vivet, F. Robin,
ASPRO-216 : A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor,
Proc. Async'98, March-April 1998, San Diego, CA, IEEE CS Press, pp. 22-31.
MU:
- W.J. Bainbridge, S.B. Furber,
Asynchronous Macrocell Interconnect Using MARBLE,
Proc. Async'98, March-April 1998, San Diego, CA, IEEE CS Press, pp. 122-132.
ACiD-WG Edited Periodic Progress Report for Publication May 1997 - April 1998
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Last altered 21st July 1998