Periodic Progress Report

(May 1999 - April 2000)

Working Group 21949 (ACiD-WG)

Asynchronous Circuit Design

MB Josephs (Project Manager)
Centre for Concurrent Systems and VLSI, School of CISM, South Bank University (SBU), London, UK
J Cortadella
Department of Software, University Polytechnic of Catalonia (UPC), E
SB Furber
Department of Computer Science, University of Manchester (MU), UK
L Lavagno
Department of Electrical, Management and Mechanical Engineering, University of Udine (UU), I
M Renaudin
TIMA Laboratory, National Polytechnic Institute of Grenoble (INPG), F
J Sparsø
Department of Information Technology, Technical University of Denmark (DTU), Lyngby, DK
JT Udding
Department of Computing Science, University of Groningen (RuG), NL
K van Berkel
IC Design Centre, Philips Research Laboratories (PRL), Eindhoven, NL
T Verhoeff
Department of Mathematics and Computing Science, Eindhoven University of Technology (TUE), NL
AV Yakovlev
Department of Computing Science, University of Newcastle (NU), UK

Introduction
Technology Transfer
ACiD-WG Workshop, Grenoble
Async 2000
SBU - PRL Project
Sixth and Seventh UK Asynchronous Forums
Meeting in Newcastle
Publications

Introduction

The specific objectives of the Working Group in the Fourth Framework, as stated in Annex 1 of Contract No. 21949, were to

facilitate the work of the ten European scientists who form its Technical Management Committee (TMC) and their research teams by providing financial support for European and international travel;
organise European workshops for regular exchange of information and discussion between teams, covering the costs of invited speakers where appropriate;
organise European teaching and training activities aimed at university students, young researchers and practising engineers;
support the research work or training of European scientists and engineers from other teams by inviting them to our events, covering their costs where appropriate;
support a European bid to host Async'97, the Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, with an offer of 10K ECU of financial sponsorship (Async'94 and Async'96 were held in Utah, USA, and in Aizu, Japan, respectively).

We also committed ourselves to make every effort to establish and build upon contacts within the European semiconductor industry and other related industries with a view to better understanding their needs and to facilitating technology transfer.

In this report we describe the activities of the Working Group during its fourth (and final) year of operation under this contract. Travel and subsistence costs were claimed (objective 1) for European travel to

our workshop
Async2000
miscellaneous meetings.

In the first three years, workshops were hosted by RuG, PT and NU; this year a workshop was hosted by INPG (objective 2). Objective 3 was met in 1997 when a summer school was hosted by DTU. In each case, financial support was given to European participants who were not members of the Working Group (objective 4). Objective 5 was met when TUE hosted Async 97 and was surpassed when UPC hosted Async 99.

At the end of this year, all current members (with the exception of RuG) hope to continue their involvement in ACiD-WG under the Fifth Framework Programme. Udding resigned from RuG this year and his student, Mallon, successfully defended his PhD thesis. (It is noteworthy that Mallon has had papers accepted at the last four Async symposia.)

Technology Transfer

This year has seen two changes in industrial affiliation to ACiD-WG. MIPS Denmark Development Center joined because asynchronous circuit design may be of use to them in the design of low-power IP blocks. The company has been collaborating with DTU, including sponsoring MSc projects in this area.

The other change was that former industrial affiliate, Cogency Technology, closed its European operation and appears to have moved away from asynchronous circuit design. (In contrast, Motorola's Semiconductor Products Sector invested in Theseus Logic, a US company founded in 1996 that has been developing an asynchronous circuit design flow based on commercial CAD tools. Motorola and Theseus will jointly develop asynchronous versions of the former s 32-bit MCore and 8-bit microcontroller architectures. A more recent US start-up, Asynchronous Digital Design, Inc., is looking to introduce the semiconductor industry to a new breed of high-performance processors.)

Sustained interest in asynchronous circuit design among industrial affiliates is evidenced by Infineon Technologies, STMicroelectronics, CSEM and Matra British Aerospace joining the consortium that is set to continue ACiD-WG into the Fifth Framework Programme. Other companies that will become members are AT&T Laboratories, Neural Networks Technologies and IHP.

Students who completed their research training under Renaudin have gone to work for CSEM and STMicroelectronics, students trained by Josephs and Udding have gone to work for PRL, and a student trained under Cortadella has gone to work for Theseus. Cortadella himself will be visiting Theseus, July/August 2000, to help them integrate PETRIFY into their design flow.

Applications

On the design experiment DESCALE (contract nr. 25519), PRL, in collaboration with MAZ Hamburg and Philips Semiconductors, made a comparison of asynchronous and synchronous chips for contactless smartcards. This revealed that the former

give maximum performance for the power received
are more resilient to voltage drops
have less pronounced current peaks
give little communication interference when combined with a power regulator.

These advantages were so convincing that a product (chip for dual interface card) is being designed.

MU (with funding from OMI/DE2 and OMI/ATOM) completed the design of AMULET3i, the third generation asynchronous ARM-compatible microprocessor subsystem. It is capable of forming the core of a wide range of system-on-chip applications. Its performance and area are comparable with clocked equivalents, and its low-power and electromagnetic emission characteristics give it unique capabilities in appropriate applications. Unfortunately, the commercial partner that was to market the first product to incorporate this technology went into receivership. This has delayed exploitation, but it is expected that a product will appear in the not too distant future.

INPG has also been involved in the design of an asynchronous contactless smartcard and an asynchronous microprocessor (ASPRO), the former as a demonstrator for France Telecom R&D and the latter as a demonstrator for STMicroelectronics. INPG made use of their CHP2VHDL translation tool in the design flow. The ASPRO processor won an "Electron d'Or" award from the French publication "Electronique".

Tools

At the hands-on day that preceded Async 2000, two of the four tools selected for demonstration were MU's (TANGRAM-like) syntax-directed translation tool BALSA and UPC's logic synthesis tool PETRIFY. The other two were ATACS (University of Utah) and MINIMALIST (Columbia University).

MU continue to maintain their LARD HDL. They developed a model of AMULET3i in LARD with which they were able to simulate the execution of ARM code. LARD also provides the simulation engine for BALSA.

DTU have released a graphical front-end to PETRIFY, which was demonstrated at the ACiD-WG Workshop in Grenoble. At the same workshop, SBU presented a formal language (delay-insensitive sequential processes) and an algorithm for its translation into Petri nets. This is being incorporated into SBU's tool DI2PN, which also provides a front-end to PETRIFY.

DTU have gained further experience of practical design using VHDL extended with (concurrent) channel communication, and are beginning an investigation into high-level synthesis from control-data-flow-graphs. Meanwhile, Politecnico di Torino and UU proposed at Async 2000 an asynchronous synthesisable subset of Verilog, and released an experimental version of a tool that supports their design methodology.

UPC have started a project on formal verification of timed verification, with support from Intel Corporation. A Russian researcher, who participated in the ACiD-WG meeting in St. Petersburg in 1998, has been recruited on to that project.

Dissemination

Sparsø delivered a 12-lecture intensive course on asynchronous circuit design at DIMES, Delft University of Technology, on May 3-7, 1999. He is to use the material as the basis of a new course for postgraduate students at DTU.

Furber spoke on "Asynchronous chip design to drive phone miniaturisation" at Mobile Silicon '99 in London, June 1999.

Piguet and Heer, representing industrial affiliates CSEM and Infineon, respectively, once again contributed to a EuroPractice advanced course on "Digital IC Design" at EPFL, Switzerland, September 1999. The course will be held again in August/Septmber 2000.

UPC, UU and NU developed a tutorial on "Hardware Design and Petri nets" (a significant part of which is on asynchronous design) for presentation at the Petri net conference in Aarhus, Denmark, June 2000.

Renaudin devised a course of lectures on asynchronous circuits and systems for the International Summer School on Advanced Microelectronics-Grenoble "MIGAS", June/July 2000, of which he is scientific co-chair. This year the theme of the Summer School is "Microelectronics for Telecommunications: Managing High Complexity and Mobility".

The Project Manager continues to keep up to date the home page of ACiD-WG on the World Wide Web at URL "http://www.scism.sbu.ac.uk/ccsv/ACiD-WG/".

ACiD-WG Workshop, Grenoble, France, 31 January - 1 February 2000

53 people attended the Grenoble workshop, a 15% increase on the Newcastle workshop, which itself had 50% more participants than the Turin and Groningen workshops. 22 of the attendees were from France (considerably more than at any previous event), with the rest from Denmark, Finland, Germany, Israel, Italy, the Netherlands, Russia, Spain, Switzerland and the United Kingdom, representing 30 organisations in all. These included 8 out of the 10 current members of ACiD-WG, as well as CSEM, IHP, Infineon Technology and STMicrolectronics.

The programme consisted of 16 technical presentations divided into 6 sessions (3 on methodologies and tools and 3 on design), plus a demonstration session. One of the design sessions was devoted to smartcards. Opportunities for asynchronous circuit design to help reduce smartcard fraud were also suggested and may be investigated on a Fifth Framework project.

STMicroelectronics described the synchronous design of a video encoder/decoder, highlighting such issues as asynchronous tasks performed by processors, clock-gating and clock-skew management, and interfacing to an asynchronous world. PRL also talked about synchronous design, comparing synchronous and asynchronous implementations of the handshake circuits generated by their TANGRAM compiler. Further research performed at PRL (in collaboration with SBU) was reported, this time comparing synchronous and asynchronous DSP cores. Finally, many of the methodologies and tools presentations were concerned with asynchronous circuit design using VHDL and using Signal Transition Graphs.

The proceedings of this workshop are available both as a TIMA Technical Report (ISBN: 2-913329-43-8) and on the World Wide Web at URL "http://tima-cmp.imag.fr/tima/cis/cis.html". Copies were distributed to all industrial affiliates of ACiD-WG.

Async 2000, Eilat, Israel, 4-6 April 2000

The Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems took place in Israel, which has entered into an Association Agreement with the EU. ACiD-WG was not in a position to provide financial support to the organisers (Technion), but is still listed as a sponsor on the cover of the Proceedings (published by the IEEE Computer Society Press).

Attendance was reasonable, though lower than previous years. Furber was programme co-chair, together with Kishinevsky (Intel). All members of ACiD-WG (apart from RuG) were represented on the Programme Committee and all (apart from TUE) sent delegates to the event. There were 46 submissions, and 8 of the 20 accepted were from members of ACiD-WG. Although fewer papers were submitted than in previous years, the quality of the programme remained high.

The best paper award was won by Nowick (Columbia University) and his student, Singh for "High-throughput asynchronous pipelines for fine-grain dynamic datapaths". Singh had benefitted from visiting MU during the year.

SBU-PRL Project, Eindhoven, August - November 1999

Pessolano, a student of Josephs, was able to spend several months at PRL, thanks to the financial support of ACiD-WG. He applied ideas from his postgraduate research into "asynchronous-friendly" computer architecture to the DSP domain, and gained experience with TANGRAM. Immediate results include a joint patent application and joint papers, including a presentation at the Grenoble workshop. A report is linked to the ACiD-WG home page.

J. Garside, W. Bainbridge, A. Bardsley et al, AMULET3i - An Asynchronous System-on-Chip, Proc. Async 2000, April 2000, Eilat, IEEE CS Press, pp. 162-175.
M.J.G. Lewis, L.E.M. Brackenbury, An Instruction Buffer for a Low-Power DSP, Proc. Async 2000, April 2000, Eilat, IEEE CS Press, pp. 176-186.
P. A. Riocreux, M. J. G. Lewis, L. E. M. Brackenbury, Power reduction in self-timed circuits using early-open latch controllers, IEE Electronics Letters, Vol.36, pp.115-116, January 2000.
S-H. Chung, S.B. Furber, The design of the control circuit for an asynchronous instruction prefetch unit using signal transition graphs, Proc. HWPN'99, June 1999, Williamsburg, pp. 131-147.

NU:

A. Bystrov, D. Kinniment, A. Yakovlev, Priority Arbiters, Proc. Async 2000, April 2000, Eilat, IEEE CS Press, pp. 128-137.
F. Xia, A. Yakovlev, D. Shang, A. Bystrov, A. Koelmans, D. Kinniment, Asynchronous Communication Mechanisms using Self-timed Circuits, Proc. Async 2000, April 2000, Eilat, IEEE CS Press, pp. 150-159.
D. J. Kinniment, A.V. Yakovlev, B. Gao, Synchronous and Asynchronous A-D Conversion, IEEE Trans. on VLSI Systems, Vol. 8 No. 2, Apr. 2000, pp. 217-219.
M. Pietkiewicz-Koutny, The synthesis problem for Elementary Net Systems with Inhibitor Arcs, Fundamenta Informaticae, R.Janicki (ed.), Volume 40, Number 2-3, November-December 1999, 251-283.
D.J. Kinniment, A.V. Yakovlev, Low power, low noise micropipelined flash A-D converter, IEE Proc. Circuits, Devices and Systems, vol. 146, no.5, October 1999, pp. 263-267.
L. Lloyd, K. Heron, A. Yakovlev, A.M. Koelmans, Asynchronous microprocessors: from high level model to FPGA implementation, Journal of Systems Architecture vol. 45 (1999), pp. 975-1000, Elsevier.
A. Bystrov, A. Yakovlev, Ordered arbiters, Electronics Letters, 27th May 1999, Vol. 35, No. 11, pp. 877-879.

NU and UU:

A. Yakovlev, L. Gomes and L. Lavagno (Eds.), Hardware Design and Petri Nets, Kluwer Academic Publishers, Boston, ISBN 0-7923-7791-5, March 2000, 344 pp.
A. Yakovlev and L. Lavagno (Eds.), Proc. HWPN'99, June 21, 1999, Williamsburg.

NU, UU, UPC and Theseus:

H. Saito, A. Kondratyev, J. Cortadella, L. Lavagno, A. Yakovlev, What is the cost of Delay Insensitivity?, Proc. IEEE/ACM IC-CAD, San Jose (USA), Nov. 1999, pp. 316-323.

NU, UU, UPC, Theseus and Intel:

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, E. Pastor , A. Yakovlev, Decomposition and Technology Mapping of Speed-Independent Circuits Using Boolean Relations, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 9, Sept. 1999, pp. 1221-1236.
A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, A. Yakovlev, Automatic synthesis and optimization of partially specified asynchronous systems, Proc. 36th DAC, New Orleans (USA), June 1999, pp. 110-115.

UPC:

E. Pastor, J. Cortadella and M.A. Pena, Structural Methods to Improve the Symbolic Analysis of Petri Nets, ATPN 99, LNCS 1639, pp. 26-45, Springer Verlag, June 1999.

UPC and Theseus:

M.A. Pena, J. Cortadella, A. Kondratyev, E. Pastor, Formal verification of safety properties in timed circuits, Proc. Async 2000, April 2000, Eilat, IEEE CS Press, pp. 2-11.

UPC and Intel:

J. Cortadella, M. Kishinevsky, S.M. Burns, K. Stevens, Synthesis of asynchronous control circuits with automatically generated relative timing assumptions, Proc. IEEE/ACM IC-CAD, San Jose (USA), Nov. 1999, pp. 324-331.

UPC, Intel and Technion:

K. Stevens, S. Rotem, S. M. Burns, J. Cortadella, R. Ginosar, M. Kishinevsky and M. Roncken, CAD directions for High Performance Asynchronous Circuits, Proc. 36th DAC, New Orleans (USA), June 1999, pp 116-121.

Politecnico di Torino and UU:

I. Blunno, L. Lavagno, Automated synthesis of micro-pipelines from behavioral Verilog HDL, Proc. Async 2000, April 2000, Eilat, IEEE CS Press, pp. 84-92.
I. Blunno, L. Lavagno, Towards a language-based design flow for asynchronous circuits, Proc. International Workshop on Logic Synthesis, June 1999.

INPG, STMicrolectronics and CSEM:

M. Renaudin, P. Vivet, F. Robin, ASPRO : an Asynchronous 16-Bit RISC Microprocessor with DSP Capabilities, ESSCIRC'99, Duisburg, September 21-23, pp. 428-431, 1999.

RuG:

W.C. Mallon, Theories and Tools for the Design of Delay-Insensitive Communicating Processes, PhD Thesis, January 2000, Rijksuniversiteit Groningen, ISBN: 90-367-1180-0.
W.C. Mallon, On Directed Transformations of Delay-Insensitive Specifications, Proc. Async 2000, April 2000, Eilat, IEEE CS Press, pp. 12-22.

PRL, MAZ Hamburg and Philips Semiconductors:

J. Kessels, T. Kramer, G. den Besten, A. Peeters, V. Timm, Applying Asynchronous Circuits in Contactless Smart Cards, Proc. Async 2000, April 2000, Eilat, IEEE CS Press, pp. 36-44.

PRL and Sun:

C.H. (Kees) van Berkel, C.E. Molnar, Beware the Three-Way Arbiter, IEEE Journal of Solid-State Circuits, 34(6), pp. 840-848, June 1999.

TUE:

J. Rutten, Synthesis of Asynchronous Burst-Mode Finite State Machines, PhD Thesis, Eindhoven University of Technology, April 2000.

SBU:

M. B. Josephs, D. P. Furey, Delay-insensitive interface specification and synthesis, Proc. DATE 2000, March 2000, pp. 169-173.
M.B. Josephs, Models of Asynchronous Computation, Proc. FDL 99, September 1999, Lyon, pp. 472-476.
F. Pessolano, Introducing Delay Probability Graphs with the Design of a 32-bit Asynchronous ALU, Proc. ECS 99, September 1999, Bratislava.
F. Pessolano, M. Bush, D. Protheroe, The Design of the Gravity Asynchronous Processor Core, Proc. ECCTD 99, August 1999, Stresa.
F. Pessolano, D. Protheroe, M. Bush, Data-Dependent Clocked Logic, Proc. ECCTD 99, August 1999, Stresa.
F. Pessolano, Heterogeneous Clustered Processors: Organization and Design, Proc. Euro-Par 99, August 1999, Toulouse, LNCS 1685, pp. 1296-1300.